Running a riscv VM in qemu
I took the steps from:
The blog post has more details about the commands below.
- Install qemu riscv, boot and rom
- Download qemu debian sid image
- Unzip
- Boot qemu riscv image
- Log with ssh
sudo apt-get install qemu-system-misc u-boot-qemu opensbi
wget "https://gitlab.com/api/v4/projects/giomasce%2Fdqib/jobs/artifacts/master/download?job=convert_riscv64-virt" -O debian-rv64.zip
mkdir debian-rv64
cd debian-rv64
unzip ../debian-rv64.zip
cd dqib_riscv64-virt
qemu-system-riscv64 -machine 'virt' -cpu 'rv64' -m 1G -device virtio-blk-device,drive=hd -drive file=image.qcow2,if=none,id=hd -device virtio-net-device,netdev=net -netdev user,id=net,hostfwd=tcp::2222-:22 -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf -kernel /usr/lib/u-boot/qemu-riscv64_smode/uboot.elf -object rng-random,filename=/dev/urandom,id=rng -device virtio-rng-device,rng=rng -nographic -append "root=LABEL=rootfs console=ttyS0"
# In another terminal
chmod 600 ssh_user_ed25519_key
ssh debian@localhost -p 2222 -i ssh_user_ed25519_key
In the zip file, there is readme.txt for help.
The gcc predefined macro to detect riscv target at compile time is:
__riscv
I found it by running this command:
gcc -Wp,-dM -E -c - < /dev/null | grep risc|less
#define __riscv 1
#define __riscv_atomic 1
#define __riscv_cmodel_medany 1
#define __riscv_mul 1
#define __riscv_misaligned_slow 1
#define __riscv_muldiv 1
#define __riscv_xlen 64
#define __riscv_fsqrt 1
#define __riscv_m 2000000
#define __riscv_fdiv 1
#define __riscv_a 2001000
#define __riscv_c 2000000
#define __riscv_d 2002000
#define __riscv_f 2002000
#define __riscv_i 2001000
#define __riscv_zicsr 2000000
#define __riscv_compressed 1
#define __riscv_float_abi_double 1
#define __riscv_flen 64
#define __riscv_arch_test 1
#define __riscv_div 1
#define __riscv_zifencei 2000000
I added #ifdef __riscv in libsheepy and the latest sheepy version supports riscv cpus.
The instructions for the riscv cpus are 32bit or longer and there is a compressed mode in which some instructions are 16bit.
The encoding is described in the riscv specification
in section 1.5 Base Instruction-Length Encoding.
3 2 1
1098765432109876 5432109876543210
xxxxxxxxxxxxxxxx xxxxxxxxxxxbbb11 32-bit (bbb != 111)
When bit 0 and 1 are not 11, it is a 16bit instruction.
RISCV 32bit
Build a linux kernel and busybox.
git clone https://git.buildroot.net/buildroot
make qemu_riscv32_virt_defconfig
# make menuconfig to configure
make
qemu-system-riscv32 \
-M virt -nographic \
-bios output/images/fw_jump.elf \
-kernel output/images/Image \
-append "root=/dev/vda ro" \
-drive file=output/images/rootfs.ext2,format=raw,id=hd0 \
-device virtio-blk-device,drive=hd0 \
-netdev user,id=net0 -device virtio-net-device,netdev=net0
Links
How to run Debian on riscv 32bit (the apt repositories dont exist anymore)
#riscv #qemu